1. Field
This patent document relates to a memory device.
2. Description of the Related Art
Memory devices such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) include a large number of memory cells. With the rapid increase in integration of memory devices, the number of memory cells included in the memory devices has also increased. Such memory cells are arranged to form an array, and the arrays are referred to as cell blocks.
The structure of memory devices may be divided into folded bit line structures and open bit line structures.
The folded bit line structure includes a driving bit line and a reference bit line, which are arranged in the same cell block, based on a bit line sense amplifier arranged in the core region of the memory device. The driving bit line refers to a bit line in which data are driven, and the reference bit line refers to a bit line which serves as a reference during an amplification operation. Thus, since the same noise is reflected in the driving bit line and the reference bit line, noise generated from the driving bit line and the reference bit line may cancel out. Through this cancellation of noise, the folded bit line structure helps support stable device operation. The open bit line structure includes a driving bit line and a reference bit line which are arranged in different cell blocks, based on a bit line sense amplifier. Thus, since noise generated in the driving bit line is different from noise generated in the reference bit line, the open bit line structure is more vulnerable to such noise.
In the folded bit line structure, a unit memory cell is designed to have an 8F2 structure, and in the open bit line structure, a unit memory cell is designed to have a 6F2 structure. This unit memory cell structure is a factor that determines the size of a memory device. Based on the same data storage capacity, a memory device having the open bit line structure may be designed smaller than a memory device having the folded bit line structure.
FIG. 1 is a diagram describing a memory device having the folded bit line structure.
Referring to FIG. 1, the memory device having the folded bit line structure may include first and second cell blocks 110 and 120 and a sense amplifier 130.
Each of the first and second cell blocks 110 and 120 may include a plurality of memory cell arrays for storing data. The first cell block 110 may include a first bit line and bit line bar BL1 and BLB1, and the second cell block 120 may include a second bit line and bit line bar BL2 and BLB2.
The sense amplifier 130 senses and amplifies voltage levels of the first bit line and bit line bar BL1 and BLB1 or senses and amplifies voltage levels of the second bit line and bit line bar BL2 and BLB2, in response to first and second bit line separation signals BISH and BISL. The sense amplifier 130 includes transistors which are turned on in response to the first and second bit line separation signals BISH and BISL and a latch-type sense amplification circuit which performs a sense amplification operation.
As described above, the folded bit line structure includes a driving bit line and a reference bit line which are arranged in one cell block. For example, when the first bit line separation signal BISH is activated to a logic high level and the second bit line separation signal BISL is deactivated to a logic low level, data is transmitted to the first bit line BL1 or the first bit line bar BLB1 along an activated word line WL. At this time, a bit line to which the data is transmitted becomes the driving bit line, and a bit line paired with the bit line to which the data is transmitted becomes the reference bit line. Then, the sense amplification circuit of the sense amplifier 130 senses the data transmitted through the first bit line and bit line bar BL1 and BLB1, and amplifies the sensed data to voltage levels corresponding to a pull-up power supply voltage RTO and a pull-down power supply voltage SB which are supplied as power to the sense amplification circuit.
FIG. 2 is a diagram describing a memory device having the open bit line structure.
Referring to FIG. 2, the memory device having the open bit line structure includes first and second cell blocks 210 and 220 and a sense amplifier 230.
Each of the first and second cell blocks 210 and 220 includes a plurality of memory cell arrays for storing data. The first cell block 210 includes a first bit line BL1 arranged therein, and the second cell block 220 includes a first bit line bar BLB1 arranged therein. The sense amplifier 230 serves to sense and amplify voltage levels of the first bit line and bit line bar BL1 and BLB1. The sense amplifier 230 has the same structure as the sense amplification circuit of FIG. 1.
As described above, the open bit line structure includes a driving bit line arranged in one cell block and a reference bit line arranged in another cell block. For example, when data is driven to the first bit line BL1, the first bit line bar BLB1 arranged in the second cell block 220 becomes the reference bit line, and when data is driven to the first bit line bar BLB1, the first bit line BL1 arranged in the first cell block 210 becomes the reference bit line.
Thus, the open bit line structure does not require additional transistors for separately operating the sense amplifier 230 for the first cell block 210 and the second cell block 220, and the sense amplifier 230 needs only to sense and amplify the voltage levels of the first bit line and bit line bar BL1 and BLB1 according to the activated word line WL.
However, the memory device having the open bit line structure requires minimizing a loading difference of the bit line sense amplifier arranged at the outermost part.